| 基于FPGA的IP协议解析的研究与实现 |
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| 引用本文： | 王文豪,李志祥,张媛,周永学.基于FPGA的IP协议解析的研究与实现[J].军械工程学院学报,2012(2):63-66. |
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| 作者姓名： | 王文豪 李志祥 张媛 周永学 |
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| 作者单位： | [1]军械工程学院科研部 [2]计算机工程系 [3]教练团 [4]院办公室,河北石家庄050003 |
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| 摘 要： | 阐述了IP协议解析硬件实现算法，采用内容寻址存储器CAM（ContentAddressableMemory）来管理已接收的IP分片，用片外扩展DDRSDRAM作为大容量IP分片重组缓存区，基于FPGA平台实现了IP协议的硬件解析，数据传输频率可达130MHz，吞吐率在1Gbps以上．
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| 关 键 词： | 协议解析 IP协议 FPGA |
Research and Implementation of IP Protocol Of f load Based on FPGA |
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| WANG Wen-hao,LI Zhi-xiang,ZHANG Yuan,ZHOU Yong-xue.Research and Implementation of IP Protocol Of f load Based on FPGA[J].Journal of Ordnance Engineering College,2012(2):63-66. |
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| Authors: | WANG Wen-hao LI Zhi-xiang ZHANG Yuan ZHOU Yong-xue |
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| Institution: | 1. Department of Scientific Research 2. Department of Computer Engineering 3. Training Regiment 4. Office of OEC College, Ordnance Engineering College, Shijiazhuang 050003, China) |
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| Abstract: | This paper introduces an algorithm of IP protocol offloading which is implemented based on FPGA with CAM（Content Addressable Memory） as the main part of received IP frag- ment scheduling module,DDR SDRAM as the large buffer of IP de-fragmentation. The data can transfer at frequency up to 130 MHz with throughput as high as 1 Gbps. |
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| Keywords: | protocol offload IP protocol FPGA |
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