| 一种基于VLIW DSP架构的高性能取指流水线 |
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| 引用本文： | 杨惠,陈书明,万江华.一种基于VLIW DSP架构的高性能取指流水线[J].国防科技大学学报,2011,33(4):102-106. |
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| 作者姓名： | 杨惠 陈书明 万江华 |
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| 作者单位： | 国防科技大学计算机学院,湖南长沙,410073 |
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| 基金项目： | 国家科技重大专门资助项目(2009ZX01034-001-006) |
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| 摘 要： | 以超长指令字(VLIW)数字信号处理器(DSP)作为平台,针对现有提高单线程取指流水线效率的方法中存在的弊端,提出了一种高性能的取指流水架构.该架构支持无效取指的检测与作废,从而降低不必要的cacbe访问,减少取指流水停顿周期,该结构还引入专用硬件支持编译调度的循环软流水,有效提高指令并行性,降低代码存储空间,由此释放...
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| 关 键 词： | 数字信号处理器 无效取指 软件流水 循环缓冲 |
| 收稿时间： | 2010/11/29 0:00:00 |
A High-performance Fetch Pipeline Based On the VLIW DSP Architecture |
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| YANG Hui,CHEN Shuming and WAN Jianghua.A High-performance Fetch Pipeline Based On the VLIW DSP Architecture[J].Journal of National University of Defense Technology,2011,33(4):102-106. |
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| Authors: | YANG Hui CHEN Shuming and WAN Jianghua |
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| Institution: | YANG Hui,CHEN Shu-ming,WAN Jiang-hua(College of Computer,National Univ.of Defense Technology,Changsha 410073,China) |
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| Abstract: | For the drawbacks existent in single-thread fetch pipeline to improve the efficiency,a high-performance fetch pipeline structure is proposed in this paper based on the platform of the VLIW digital signal processor(DSP).It can support the detection and void for the invalid fetch,bypass for the missing fetch,which reduces the unnecessary cache access and fetch pipeline stall.The structure also inducts dedicated hardware which supports the software pipeline of scheduled compilation to improve the parallelism o... |
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| Keywords: | digital signal processor invalid instruction fetch software pipeline loop buffer |
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