FPGA参数化多标准高吞吐率基4 Viterbi译码器

为了同时达到高性能和灵活性的目标，提出了一种基于FPGA的参数化多标准自适应基4 Viterbi译码器。译码器采用3-9可变约束长度，1/2、1/3可变码率，支持任意截断长度的纠错译码，并采用了码字无符号量化、加比选单元设计优化和归一化判断逻辑分离策略优化了关键路径设计，提高了译码器工作频率。实验结果表明，该译码器能根据用户设定的参数改变结构，在多种通信标准之间实现动态切换；性能达到了541Mbps，明显优于相关工作；对GPRS、WiMAX、LTE、CDMA、3G等通信标准都取得了良好的误码性能，可满足多种通信标准的译码需求。

Parameterized Multi-standard High-throughput Radix-4 Viterbi Decoder on FPGA

To achieve the goal of high performance and flexibility, this paper presents a parameterized multi-standard adaptive radix-4 Viterbi decoder with low complexity on FPGA. This decoder adopts constraint lengths ranging from 3 to 9, code rates in the range 1/2-1/3 and arbitrary truncation lengths. The unsigned quantization, ACSU optimization and normalization strategies are used to improve system throughput. It achieves low bit error ratio in multiple standards such as GPRS, WiMax, LTE, CDMA and 3G. The throughput can reach to 541Mbps, apparently superior to related works.