一种适于片上路由器的自适应缓冲调整策略

在典型的片上网络路由节点中,来自不同方向的报文被存储在相互独立的缓冲资源中。在网络负载不均衡的情况下,某些方向的报文将很快填满该方向的缓冲,而其他方向仍可能有较多的缓冲资源处于空闲状态,这样就导致了网络中的缓冲资源利用率不高,进而影响片上网络的整体性能。提出了一种自适应的片上缓冲调整策略,能够根据网络负载情况动态调节缓冲结构,有效地提高了缓冲资源的利用率。在90nmCMOS工艺下设计实现了多端口共享缓冲资源的片上网络路由器,实验结果表明,在负载不均衡的网络中,提出的路由器能够带来性能改进及功耗降低;在达到相同性能的情况下,新路由器的面积较典型路由器减少了20.3%,而其缓冲功耗节约了41%左右。

An adaptive buffer regulating scheme for on-chip routers

In the traditional Network-on-Chip routers, packets from different directions are temporarily stored in different buffer regions, and these buffering resources are independent from each other. Under non-uniform traffic patterns, buffers in some input channel will be crammed by the coming packets quickly, while the others are still in idle state. As a result, the buffers are utilized inefficiently, and it has a negative influence on the overall network performance. In this paper, an adaptive buffer regulating scheme that can be used to achieve similar performance by using less buffering resources is introduced. The VLSI implementation of a router with the buffer regulating scheme is completed under 90nm CMOS process. The experimental results show that the proposed router can bring significant performance improvement and power reduction under non-uniform traffic patterns, 20.3% area saving of the proposed router and 41% power reduction of the buffers can be achieved compared to the traditional one.