低开销的软错误免疫寄存器设计

随着工艺尺寸的逐渐缩小,集成电路中由放射性粒子引起的软错误不断增加,在设计时必须考虑由软错误引起的可靠性问题.使用软错误免疫寄存器对电路敏感部分选择性加固是降低逻辑电路软错误率简单有效的方法.总结了常用的软错误免疫寄存器结构,并使用可靠性分析方法对8种寄存器进行量化研究和比较,得出双模时空冗余寄存器具有更高的可靠度;针对现有可靠寄存器开销较大的缺点,设计了一种基于时钟延时的动态主级时空双模冗余寄存器--DMTS-DR,不仅能很好地免疫自身的SEU,还能对前级组合逻辑的SET进行有效屏蔽.与其它可靠寄存器相比,DMTS-DR的面积和延时开销都有大幅降低,在可靠性、面积和速度间实现了较好的折中.

Design of Soft Error Immune Registers with Low Overhead

Due to technology scaling, radiation-induced soft error has been increasing in VLSI systems. Designers have to consider the problem of reliability caused by soft errors. Selective hardening of vulnerable nodes in circuits using resilient registers is a prevalent solution, which can effectively reduce soft error rate of logic circuits. This paper gives a summary of some soft error immune registers, and then provides quantitative analysis and comparison in reliability of eight kinds of registers. The result concludes that temporal spatial dual modular redundancy structure shows better reliability. The existent reliable registers brings about great overhead that cannot be avoided, so tiffs paper designs a timing shift-based Dynamic Master Temporal Spatial -Dual modular redundancy egister (DMTS-DR).The experiment results show that the proposed register is not only able to immunize SEUs in itself, but can also mask SETs propagated from combinational logic efficiently. Compared to other reliable registers, area overhead and delay penalty of DMTS-DR have been reduced greatly. DMTS-DR has better tradeoff among reliability, area and speed.