基于SAT的电路错误定位方法研究进展

随着VLSI芯片复杂度不断增加,功能验证与调试已占到整个芯片设计周期的60%以上。而错误的定位往往消耗大量的时间与精力,因此迫切需要一种高效的方法诊断与定位电路中的错误。针对近年来出现的许多电路错误定位方法,介绍了电路错误诊断方法的分类与工作流程,深入分析了基于SAT的错误定位方法的基本原理;对各种算法进行了概述评论,并简要介绍了在不可满足子式求解方面所做的一些研究工作,而不可满足子式能够显著提高错误定位效率与精度;讨论了电路错误定位技术所面临的主要挑战,并对今后的研究方向进行了展望。

Research Advances in SAT-based Error Localization Methods on Circuits

With the growing complexity of VLSI designs, functional verification and debugging has become a resource-intensive bottleneck in modern CAD flows, consuming as much as 60% of the total design cycle. Error localization in circuits is difficult and time-consuming. Therefore an efficient error debugging and localization method is necessary for hardware design. Recently there are many different contributions to research on error localization in circuits. In this paper, the categories and workflow of error debugging method are firstly introduced. The fundamental principles of SAT-based error localization method are described. Then the existing algorithms are introduced and analyzed. Further, we present our research works about extract unsatisfiable subformulae, which can strongly improve the efficiency and accuracy of error localization. Finally, we discuss the current challenges, and outline the future research directions of error localization in circuits.