用于DDR3访存优化的数据缓冲机制

为提高DDR3控制器访存效率,设计了基于DDR3存储器预取访问数据长度的数据缓冲机制,将访存请求分为三种基本类型并分别排队处理,降低数据丢弃和实际动态随机访问存储器访问发生次数。针对图像和视频类应用程序的实验结果表明,相对于传统先到先服务的DDR3访存控制器,该机制取得了平均21.3%、最好51.3%的性能提升,硬件开销在可接受范围内。

DDR3 data buffering for memory access optimization

In order to improve the memory access efficiency of the DDR3 memory controller, a data buffering mechanism based on DDR3 memory access burst length is proposed in this paper. The application requests are guided into three different queues and served. The data buffering mechanism can make use of the additional data got from DRAM in one of the former request, and thus reduce the actual external DRAM access needed. Experimental on several image and video applications show that the proposed mechanism can improve the memory controller for an average 21.3% and a peak 51.3% compared with the first-come-first-serve(FCFS) baseline DDR3 memory controller, at an acceptable hardware cost.