基于FPGA的数字复接系统的同步技术研究

针对数据大容量通信时常因同步问题而面临失败的问题,分析了数字复接系统工作原理,探究了收发端高精度时钟基准同步方法在时钟校正的应用,以及位同步和帧同步的典型同步技术,并利用FPGA仿真验证了数据复接过程。数据通信依赖于收发端同步技术的建立,认为将收发端时钟同步、位同步、帧同步应用在复接系统的不同部分,能够共同作用以实现收发端数据传输的同步。卫星双向时间比对法能够有效校准收发端的高精度时钟,校准精度优于0.5 ns;数字锁相法能够自动将收发端时钟校准到同频同相的状态,有效实现位同步;在每个数据帧当中加入帧同步信号可以使收发端自动判断每一帧的数据传输状态。FPGA技术为数据仿真提供良好平台,利用其完成了过零信号的提取和数据帧同步的复接的仿真,达到预期效果。

Research on Digital Multiplex System with FPGA

For the failure caused by falling out of step in the process of high -capacity communication at any time,this article analyzes the principle of digital multiplexing,explores the application method in high-precision clock calibration and typical technologies for bit synchronization and frame synchronization in the transmission and reception unit. FPGA provides convenient software platform to simulate and verify the process of digital multiplexing. Digital communication relies on synchronous in the transmission and reception unit,this article applies clock calibration,bit synchronization and frame synchronization on different parts of system to realize the data transmission synchronization. TWTT can accomplish high-precision clock calibration,and accuracy is superior to the 0.5ns;Digital phase locked loop can automatically calibrate the state to the same frequency and phase. With the FPGA technology,this article extractes the zero signal and simulated digital multiplexing with the well result from the effect picture.