| 基于Verilog语言的边界扫描结构设计 |
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| 引用本文： | 陈圣俭,周银,徐磊,周浔,王蒙蒙.基于Verilog语言的边界扫描结构设计[J].装甲兵工程学院学报,2011,25(2):50-54. |
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| 作者姓名： | 陈圣俭 周银 徐磊 周浔 王蒙蒙 |
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| 作者单位： | 装甲兵工程学院控制工程系,北京,100072 |
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| 摘 要： | 以对74290IP核加载边界扫描结构为例,采用硬件描述语言Verilog对边界扫描结构进行了模块化设计,并进行了边界扫描测试仿真。结果表明：加载边界扫描结构后的核心逻辑能够实现功能内测试和外部互联测试。该设计方法简单可行,具有一定的通用性,为智能BIT设计、装备健康管理设计中的底层数据采集提供了技术支撑。
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| 关 键 词： | 边界扫描 Verilog IP核 可测性设计 |
Design Method of Boundary-scan Circuit Architecture Based on Verilog Language |
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| CHEN Sheng-jian,ZHOU Yin,XU Lei,ZHOU Xun,WANG Meng-meng.Design Method of Boundary-scan Circuit Architecture Based on Verilog Language[J].Journal of Armored Force Engineering Institute,2011,25(2):50-54. |
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| Authors: | CHEN Sheng-jian ZHOU Yin XU Lei ZHOU Xun WANG Meng-meng |
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| Institution: | CHEN Sheng-jian,ZHOU Yin,XU Lei,ZHOU Xun,WANG Meng-meng(Department of Control Engineering,Academy of Armored Force Engineering,Beijing 100072,China.) |
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| Abstract: | A general design method which loads the boundary-scan architecture into the logic core of circuit is proposed.Taking the IP core of 74290 as an example,the modular design of boundary-scan architecture is described by Verilog language,and the corresponding boundary-scan tests is emulated.The simulation and experiment results prove that the method is correct and feasible.The IP core with boundary-scan circuit architecture can achieve testing of the system logic and board level interconnections. |
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| Keywords: | boundary-scan Verilog IP core design for test |
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