线性规划的一种并行修正松弛算法

对求解线性规划问题的松弛算法进行了修正,在此基础上提出了一种基于cluster结构的并行算法,分析了算法的性能;基于曙光3000大规模并行计算机,给出了算法用于求解线性规划问题实例的实验结果.理论分析和实验结果表明,修正算法改进了松弛算法的实际性能,同时具有较好的并行性和稳定性,可用于求解此类大规模科学与工程规划问题的高性能计算.     

MC68HC05L9与TMS320C25并行处理在智能化仪器仪表中的应用

本文简要介绍了一种能用于智能化仪器仪表工业,由MC68HC05L9和TMS320C25两片微处理器组成的并行处理系统.该系统采用乒乓式RAM结构进行数据通讯,处理速度可达1100万次/秒.软硬件采用了抗干扰技术,具有成本低、性能高、结构简单等特点.稍加改进,也可应用于自动控制系统中.     

基于几何解算的飞机三维姿态测量方法

针对单站光测图像,提出一种基于目标形状特征的三维姿态测量方法。在已知飞机外形尺寸、光测设备成像参数以及飞机与光测设备之间距离的情况下,根据飞机参考平面(水平机翼所在平面)与成像平面平行和不平行时成像尺寸的差异,可以估计出飞机参考平面相对于成像平面的位置关系,从而得到飞机相对于摄像坐标系的三维姿态,再通过坐标转换即可得到飞机相对于大地坐标系的三维姿态。该方法充分利用了目标和成像设备的先验知识,避免了复杂的模型匹配过程,具有较好的准确度和实时性,对目标的精确控制和跟踪具有重要意义。     

Development programs for one‐shot systems using multiple‐state design reliability models

Design reliability at the beginning of a product development program is typically low, and development costs can account for a large proportion of total product cost. We consider how to conduct development programs (series of tests and redesigns) for one‐shot systems (which are destroyed at first use or during testing). In rough terms, our aim is to both achieve high final design reliability and spend as little of a fixed budget as possible on development. We employ multiple‐state reliability models. Dynamic programming is used to identify a best test‐and‐redesign strategy and is shown to be presently computationally feasible for at least 5‐state models. Our analysis is flexible enough to allow for the accelerated stress testing needed in the case of ultra‐high reliability requirements, where testing otherwise provides little information on design reliability change. © 2004 Wiley Periodicals, Inc. Naval Research Logistics, 2004     

优越的CCRP算法研究

CCRP是重要的空对地攻击方式,该文以向量三角形描述空对地瞄准,结合弹道回归多项式的三元Honer 处理,提出了一种高精度的CCRP 实时算法。     

盲提取方法在柴油机活塞-缸套撞击信号提取中的应用

讨论了盲反卷积在机械振动信号处理中的应用以及盲反卷积中常用的模型和方法,利用信号和高斯信号之间的Kullback-Leibler距离构建目标函数,提出了一种以伪并行遗传算法为优化工具的盲反卷积算法,并通过仿真验证了算法的正确性.实验也证明,该算法能成功地从柴油机机体振动信号中提取出活塞-缸套撞击信号.     

Scheduling parallel machines with inclusive processing set restrictions

We consider the problem of assigning a set of jobs to different parallel machines of the same processing speed, where each job is compatible to only a subset of those machines. The machines can be linearly ordered such that a higher‐indexed machine can process all those jobs that a lower‐indexed machine can process. The objective is to minimize the makespan of the schedule. This problem is motivated by industrial applications such as cargo handling by cranes with nonidentical weight capacities, computer processor scheduling with memory constraints, and grades of service provision by parallel servers. We develop an efficient algorithm for this problem with a worst‐case performance ratio of + ε, where ε is a positive constant which may be set arbitrarily close to zero. We also present a polynomial time approximation scheme for this problem, which answers an open question in the literature. © 2008 Wiley Periodicals, Inc. Naval Research Logistics, 2008     

Capacitated lot‐sizing and scheduling with parallel machines,back‐orders,and setup carry‐over

We address the capacitated lot‐sizing and scheduling problem with setup times, setup carry‐over, back‐orders, and parallel machines as it appears in a semiconductor assembly facility. The problem can be formulated as an extension of the capacitated lot‐sizing problem with linked lot‐sizes (CLSPL). We present a mixed integer (MIP) formulation of the problem and a new solution procedure. The solution procedure is based on a novel “aggregate model,” which uses integer instead of binary variables. The model is embedded in a period‐by‐period heuristic and is solved to optimality or near‐optimality in each iteration using standard procedures (CPLEX). A subsequent scheduling routine loads and sequences the products on the parallel machines. Six variants of the heuristic are presented and tested in an extensive computational study. © 2009 Wiley Periodicals, Inc. Naval Research Logistics 2009     

寻找无向图中全部生成树的复合支路和网络撕裂技术

将复合支路和网络撕裂技术用于寻找无向图中全部生成树的算法.给出复合支路的概念、表示方法和运算规则,以及由各个子图的全部生成树得到原图的全部生成树的方法.在图的分解和找树过程中,可以采用并行算法,从而降低了找树算法的复杂性.     

基于FPGA+DSP的双核控制器硬件设计

在设计高实时性的系统时,针对基于DSP、单片机等串行运算方式的单核控制器无法实现高实时性的问题,利用FPGA的并行运行优点构建了基于DSP+FPGA的双核控制器,以达到提高系统实时性的目的。通过分析系统总体结构,主要设计完成了系统总线构架、DA电路、CAN总线和PROM电路,然后通过软件编程来验证硬件设计。经调试分析,该系统各部分运行正常,可为研究设计高实时性的控制器提供参考和借鉴。