基于FPGA的8051 IP核的设计与应用

采用VHDL语言改进实现了一个8051 IP核,嵌入FPGA并做了测试,测试表明,其中断、定时器、串口、I/O口均达到了实用的要求,指令集与标准8051芯片指令兼容。给出了8051核的结构框图和在FPGA中嵌入8051核的设计流程。基于该IP核,实现了对GDM 12864A图形点阵液晶的控制与显示,利用其串口实现了人机交互系统设计,最后对8051核与通用8051芯片在内部资源和指令执行速度等性能指标做了比较。     

Dynamic evacuation routes for personnel on a naval ship

We propose a dynamic escape route system for emergency evacuation of a naval ship. The system employs signals that adapt to the causative contingency and the crew's physical distribution about the ship. A mixed‐integer nonlinear programming model, with underlying network structure, optimizes the evacuation process. The network's nodes represent compartments, closures (e.g., doors and hatches) and intersections, while arcs represent various types of passageways. The objective function integrates two potentially conflicting factors: average evacuation time and the watertight and airtight integrity of the ship after evacuation. A heuristic solves the model approximately using a sequence of mixed‐integer linear approximating problems. Using data for a Spanish frigate, with standard static routes specified by the ship's designers, computational tests show that the dynamic system can reduce average evacuation times, nearly 23%, and can improve a combined measure of ship integrity by up to 50%. In addition, plausible design changes to the frigate yield further, substantial improvements. Published 2008 Wiley Periodicals, Inc. Naval Research Logistics 2008     

支持高效组播的高性能路由器QoS机制研究与实现

研究并提出一种有效支持组播的高性能路由器QoS机制QoS RESM,该机制以多阈值机制为基础,考虑远程转发引擎的拥塞状态信息,引入全局控制反馈机制,有效完成了高性能路由器上支持组播的流量控制。最后描述QoS RESM在基于网络处理器的核心路由器上的实现方法。     

程控交换机硬件系统建模研究

底层功能实现模块是程控交换机多媒体仿真训练系统通用设计平台的关键部分。硬件配置是交换机工作的基础 ,是底层功能实现模块的重要组成部分。该文介绍了交换机硬件系统的建模 ,利用两种典型机型硬件实际的工作情况 ,解释并验证了所建立的通用功能流程图 ,并介绍了参数接口的管理与应用