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11.
The minimum storage‐time sequencing problem generalizes many well‐known problems in combinatorial optimization, such as the directed linear arrangement and the problem of minimizing the weighted sum of completion times, subject to precedence constraints on a single processor. In this paper we propose a new lower bound, based on a Lagrangian relaxation, which can be computed very efficiently. To improve upon this lower bound, we employ a bundle optimization algorithm. We also show that the best bound obtainable by this approach equals the one obtainable from the linear relaxation computed on a formulation whose first Chvàtal closure equals the convex hull of all the integer solutions of the problem. © 2001 John Wiley & Sons, Inc. Naval Research Logistics 48: 313–331, 2001 相似文献
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This paper examines scheduling problems in which the setup phase of each operation needs to be attended by a single server, common for all jobs and different from the processing machines. The objective in each situation is to minimize the makespan. For the processing system consisting of two parallel dedicated machines we prove that the problem of finding an optimal schedule is N P‐hard in the strong sense even if all setup times are equal or if all processing times are equal. For the case of m parallel dedicated machines, a simple greedy algorithm is shown to create a schedule with the makespan that is at most twice the optimum value. For the two machine case, an improved heuristic guarantees a tight worst‐case ratio of 3/2. We also describe several polynomially solvable cases of the later problem. The two‐machine flow shop and the open shop problems with a single server are also shown to be N P‐hard in the strong sense. However, we reduce the two‐machine flow shop no‐wait problem with a single server to the Gilmore—Gomory traveling salesman problem and solve it in polynomial time. © 2000 John Wiley & Sons, Inc. Naval Research Logistics 47: 304–328, 2000 相似文献
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介绍了迫弹电子时间引信控制系统的电路组成、工作原理及其功能,并以PIC16F873A型单片机作为控制器核心,对引信的工作过程进行控制,提高了引信的安全性和可靠性。 相似文献
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Demand forecasting performance is subject to the uncertainty underlying the time series an organization is dealing with. There are many approaches that may be used to reduce uncertainty and thus to improve forecasting performance. One intuitively appealing such approach is to aggregate demand in lower‐frequency “time buckets.” The approach under concern is termed to as temporal aggregation, and in this article, we investigate its impact on forecasting performance. We assume that the nonaggregated demand follows either a moving average process of order one or a first‐order autoregressive process and a single exponential smoothing (SES) procedure is used to forecast demand. These demand processes are often encountered in practice and SES is one of the standard estimators used in industry. Theoretical mean‐squared error expressions are derived for the aggregated and nonaggregated demand to contrast the relevant forecasting performances. The theoretical analysis is supported by an extensive numerical investigation and experimentation with an empirical dataset. The results indicate that performance improvements achieved through the aggregation approach are a function of the aggregation level, the smoothing constant, and the process parameters. Valuable insights are offered to practitioners and the article closes with an agenda for further research in this area. © 2013 Wiley Periodicals, Inc. Naval Research Logistics 60: 479–498, 2013 相似文献
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对雷达的全极化欺骗干扰技术研究 总被引:1,自引:0,他引:1
分析了3种针对单极化假目标的鉴别算法,针对单极化干扰的缺陷,提出并分析了一种干扰极化测量雷达的新技术——全极化干扰,介绍了全极化干扰技术的工作原理,并详细分析了全极化干扰机关键部件的设计。 相似文献
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从齿面接触分析的角度,分析了设计参数中心距、模数和蜗轮齿宽对一包TI蜗杆传动啮合性能的影响。结果表明:相对于理想啮合情况,在蜗轮分度圆直径一定的情况下,较大的中心距及较小的模数可以获得较理想的接触线的形状及分布;蜗轮齿宽的变化对接触线和啮合界限线的分布规律没有影响,但会影响接触线的长度。这些结论为合理选择设计参数提供了理论指导。 相似文献
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由于具有低功耗、高速度、高集成度等优点,单电子晶体管成为最有前景的纳米电子功能器件之一.但是,由于结构上的特殊性,单电子晶体管只能在低温下正常工作,该特性限制了其实用化进程.因此,研究可在室温下工作的单电子晶体管具有重要意义.在分析单电子晶体管工作机理的基础上,计算了单电子晶体管室温工作的基本条件,并实验制备出了样片.测试结果表明,所制备的单电子晶体管可在室温下表现出库仑振荡等基本特性.该研究成果将为单电子晶体管的集成实用化打下良好的基础. 相似文献
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新兴的三维静态存储器将代替二维静态存储器被广泛用于高性能微处理器中,但它依然会受到软错误的危害。为了能够快速、自动分析多层管芯堆叠结构的三维静态存储器软错误特性,搭建了三维静态存储器软错误分析平台。利用该平台对以字线划分设计的三维静态存储器和同等规模的二维静态存储器分别进行软错误分析,并对分析结果进行对比。研究结果表明二维和三维静态存储器的翻转截面几乎相同,但三维静态存储器单个字中发生的软错误要比二维静态存储器更严重,导致难以使用纠检错技术对其进行加固。静态模式下二维和三维静态存储器敏感节点均分布于存储阵列中,表明静态模式下逻辑电路不会引发软错误。 相似文献