22 nm全耗尽型绝缘体上硅器件单粒子瞬态效应的敏感区域

基于3D-TCAD模拟,研究了22 nm全耗尽型绝缘体上硅(fully depleted silicon-on-insulator,FDSOI)器件单粒子瞬态(single-event transient,SET)效应的敏感性区域。对比了使用单管和使用反相器来研究器件SET敏感性区域的方法,从而分析实际电路中重离子轰击位置对22 nm FDSOI器件SET敏感性的影响,并从电荷收集机制的角度进行了解释。深入分析发现寄生双极放大效应对重粒子轰击位置敏感是造成器件不同区域SET敏感性不同的原因。而单管漏极接恒压源造成漏极敏感性增强是导致单管与反相器中器件SET敏感区域不同的原因。修正了FDSOI工艺下器件SET敏感性区域的研究方法,与单管相比,采用反相器进行仿真,结果更符合实际情况,这将为器件SET加固提供理论指导。

Sensitive region of single-event transient in 22 nm FDSOI devices

Based on 3D-TCAD simulations, the sensitivity region of SET(single-event transient) effect in 22 nm FDSOI (fully depleted silicon-on-insulator) devices were investigated. A comparison was made between the methods of using a single transistor and using an inverter to study the sensitivity region of device SET, in order to analyze the influence of heavy ion strike position on the SET sensitivity of 22 nm FDSOI devices in actual circuits, and to explain it from the perspective of charge collection mechanism. In depth analysis reveals that the parasitic bipolar amplification effect is sensitive to the position of heavy particle strike, which is the reason for the different sensitivity of SET in different regions of the device. The increased sensitivity of the drain caused by a constant voltage source connected to the drain of a single transistor is the reason why the SET sensitive area of the device in the single transistor and inverter is different. The research method of studying SET sensitive regions of the devices under FDSOI process was improved. The simulation result of inverter is more in line with the actual situation than single transistor, which will provide theoretical guidance for SET hardening.