一种基于混合模拟的计算组合电路中软错误率的方法与工具

随着工艺尺寸的不断缩小,组合电路引起的SER(Soft Error Rates)越来越严重.针对使用HSPICE计算组合电路软错误率速度较慢以及使用传统的组合电路软错误率分析工具在对待重汇聚时计算精度不高的问题,本文提出了一种混合模拟的方法,并基于该方法实现了组合电路软错误率分析工具.该混合模拟方法使用HSPICE模拟发生重汇聚的逻辑门；使用快速的脉冲传播算法模拟其他逻辑门.模拟结果表明,该方法可以在速度和精度上达到很好的折中.通过与国际上常用的组合电路软错误率分析工具进行比较发现,在重汇聚发生较多的电路中,该混合模拟方法更能真实地反应组合逻辑中的软错误率.

A mixed-mode simulation method and tool for computing SER in combinational logic

As technology feature scales down,SER(Soft Error Rates) induced in the combinational logic wins increasing attention.A mixed-mode simulation method is proposed for computing SER in combinational logic,which is aimed at solving the slow HSPICE simulation speed and the low precise of traditional methods in treating re-convergence.A Mixed-Mode Analysis Tool for Combinational Logic based on this method was implemented.Re-convergence logic gates were simulated with HSPICE;a fast pulse propagate algorithm was used to simulate others.The simulation results illustrate that the proposed method gains a close precision to HSPICE with a faster speed.Compared with the prevalent SER analysis method,it is found that our proposed method can factually reflect the SER in combinational circuits where there are many re-convergence logic gates.