面向大规模卷积计算的多忆阻器阵列互连结构设计

针对现有多忆阻器阵列集成架构中存在的数据加载、读出效率低以及阵列协同灵活性差等问题,提出一种高效率、高灵活度的阵列互连架构。该架构所采用的数据加载策略支持多种权重映射模式下的数据复用,减少了片外数据访存需求；所采用的计算结果读出网络支持多个处理单元灵活组合实现不同规模卷积运算,以及计算结果的快速累加读出,进而提升了芯片灵活性和整体算力。在NeuroSim仿真平台上运行VGG-8网络进行的仿真实验表明,与MAX²神经网络加速器相比,在仅增加6%面积开销的情况下,取得了146%的处理速度提升。

Multi-memristor-array interconnection structure design for large scale CNN acceleration

To address the problems of inefficient data loading and readout and poor flexibility of array collaboration in existing multi-memristor-array, a highly efficient and flexible multi-array interconnection architecture was proposed. The data loading strategy of the architecture supports data reuse in multiple weight mapping modes, reducing the need for off-chip data access; the readout network supports flexible combination of multiple processing units to achieve different scales of convolutional operations, as well as fast accumulation and readout of computation results, thus improving chip flexibility and overall computing power. Simulation experiments performed on the NeuroSim platform with running VGG-8 networks indicate a 146% increase in processing speed than that of the MAX² neural network accelerator, with only a 6% increase in area overhead.