高速SpaceFibre总线节点的系统设计

为了实现SpaceFibre总线节点的高效数据传输,针对网络协议中关键问题和技术提出了一种基于现场可编程门阵列(Field Programmable Gate Array,FPGA)的SpaceFibre总线节点系统设计方案.其中,采用了轮询仲裁算法,解决了多路虚拟通道中流量控制字的申请冲突;设计了基于服务质量机制的高...

System design of high-speed SpaceFibre node

In order to achieve efficient data transmission of SpaceFibre node, a system design scheme of SpaceFibre node based on FPGA (field programmable gate array) was proposed aiming at the key problems and technologies in network protocols. The polling and arbitration algorithm was adopted to solve the flow control token words application conflict of multiple virtual channels. An efficient processing state machine based on QoS (quality of service) mechanism was designed, which can realize QoS scheduling for multiple virtual channels. A parallel partitioned storage architecture and a resend control algorithm were proposed, which can realize efficient error recovery based on FDIR (fault detection isolation and recovery) mechanism. Different parallel processing schemes were designed for cyclic redundancy check of various data formats and calculation of pseudo-random sequence. A simulation platform was built by ModelSim to test the function simulation of the node system, and the system verification was completed on Virtex-6 FPGA. The results show that the function of SpaceFibre bus node can be realized, and the serial transmission speeds up to 3.125 Gbit/s, which can meet the demand of high-speed data transmission.