流水的浮点倒数近似值运算部件的设计与实现

在部分低精度浮点运算应用中,需要流水的浮点倒数近似值运算。本文基于SRT-4算法设计并实现了一种流水的浮点倒数近似值运算部件。该部件采用6级流水线结构,运算结果精度至少为8位有效尾数。为了支持对非规格化浮点数的硬件处理,还设计并实现了改进版,有利于进一步提高浮点倒数近似值运算的性能。改进版采用8级流水线结构,新增了源操作数预规格化和结果后规格化功能模块,可以实现对非规格化浮点数的硬件处理。经过逻辑综合评估,改进版的硬件开销是面积在合理范围内增加19.23%,且对时序没有明显影响,可以满足预期的1.6 GHz频率设计目标。

Design and implementation of pipelined floating-point reciprocal approximation operation unit

In some low precision applications, pipelined floating-point reciprocal operation is required actually. Based on SRT-4 algorithm, a pipelined floating-point reciprocal operation unit is designed and implemented, which is constructed as a 6-stage pipeline unit, resulting an 8-bit valid fractions. In order to support hardware process of denormal numbers, the unit is improved to get higher performance, which is constructed as a 8-stage pipeline unit, adding source operand pre-normalization and result post-normalization function components and supporting hardware process of denormal numbers. After logic synthesis, the area of the unit increases by 19.23%, which is reasonable. The timing of the unit is not affected obviously and can meet the expected frequency goal of 1.6GHz.