基于准循环双对角阵的LDPC码编码算法研究*

针对校验矩阵形如准循环双对角阵的结构化LDPC码,对比研究了两类高效的编码算法：矩阵分解编码算法和分项累加递归编码算法,指出了两种算法从实现角度是等效的,但分项累加递归编码算法推导更为直观,且便于硬件并行实现。基于分项累加编码算法,提出了一种适合准循环双对角LDPC码的部分并行编码结构,设计实现了IEEE 802.11n标准中的LDPC码编码器。FPGA实现结果表明,所设计的LDPC编码器硬件开销较少,信息比特吞吐率最高能达到13Gbps。

Research on Encoding Algorithms for QC-LDPC Codes with Dual-diagonal Parity Check Matrix

Two efficient encoding algorithms, matrix decomposition encoding algorithm and cumulative recursion encoding algorithm, for the LDPC codes based on quasi-cyclic dual-diagonal parity check matrix were studied. This paper point out that the two algorithms from the implementation point of view is equivalent, and the cumulative recursion encoding algorithm is straightforwardly facilitate to hardware parallel implementation. A partly parallel encoding architecture is proposed for the QC-LDPC codes with dual-diagonal parity check matrix. The LDPC encoder compatible with IEEE 802.11n standard is designed. FPGA implementation results show that the hardware overhead of the proposed LDPC encoder is low, while its throughput can reach up to 13Gbps.