基于矩阵乘法的高速卫星成形滤波器的FPGA实现

根据高速8PSK卫星调制器的要求,针对数字化基带成形滤波的信号处理特点,文中提出一种基于矩阵乘法的高速卫星成形滤波器设计方法及基于查找表的硬件实现方案。该方法将成形滤波直接抽象为矩阵乘法的运算,将多个卷积相乘项相加后再量化,减少了量化次数,提高了量化信噪比。用片内的BLOCK-RAM精心设计查找表,在8万门的芯片VIRTEX2-80中就能实现此方案。MODELSIM的时序仿真结果表明,可支持高达200Mbps的输入数据,满足卫星通信高速成形的要求,并针对未来更高速率的成形滤波器给出了一种通用硬件实现方法。

Design of shaping filter based on matrix multiplication in the satellite high-speed transmission and look-up table implementation

Aimed at the signal processing characteristics of digitally-implemented base-band shaping,this paper proposes a design method of high speed satellite shaping filter based on matrix multiplication according to the demand for high speed 8PSK modulator and the hardware implementation scheme based on look-up table.Abstracting matrix multiplication from base-band shaping,the algorithm ould be realized in the FPGA of small scale.The project has been implemented in the VIRTEX2-80 of XILINX corporation and has proved correct through MODELSIM timing simulation.This paper presents a general hardware implementation way of the future high speed shaping filter in the end.